Non-volatile nanocrystal transistor memory cells are known. For example, U.S. Pat. No. 6,690,059 to B. Lojek describes a non-volatile memory transistor that uses a floating gate as a charge storage region, transferring charge through a tunneling barrier to nanocrystals. The device relies on a separate charge reservoir for charge supply, while the substrate is doped for conductivity between source and drain electrodes. By pulling charge from the charge reservoir to a separated nanocrystal layer, the electrostatic properties of the nanocrystal layer are modified, influencing a subsurface channel between source and drain in a MOS transistor. The nanocrystals are used to modify electrostatic properties of a separated region and then directly influence channel behavior in the usual way, characteristic of a MOS transistor. In the simplest mode of operation, a threshold may be established for charge transfer from the charge supply layer to the nanocrystal layer and this threshold is similar to the threshold of non-volatile memory transistors. However, further voltage changes will cause further electron transitions from the charge supply layer to the nanocrystal layer whereby the conductivity of the channel is changed in a stepwise manner, like modulation. Reverse voltages will cause depletion of the nanocrystal layer, driving electrons from the nanocrystal layer back to the charge supply layer. Conduction between source and drain amplifies the gate voltage in the amplifier mode or senses the pinch-off characteristic in the memory mode.
In U.S. Pat. No. 6,808,986 Rao et al describe a nanocrystal layer made using chemical vapor deposition. In U.S. Pat. No. 6,344,403 Madhukar et al describe a similar nanocrystal growth procedure.
An object of the invention is to provide a uniform, high density nanocrystal layer for more efficient discrete charge trapping in a memory transistor.